High Level Synthesis of Asics Under Timing and Synchronization Constraints by Giovanni Demicheli, David C. Ku

High Level Synthesis of Asics Under Timing and Synchronization Constraints

The Springer International Engineering and Computer Science

Giovanni Demicheli, David C. Ku

294 pages missing pub info (view editions)

nonfiction art computer science design technology informative medium-paced
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Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints a...

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