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Hierarchical Modeling for VLSI Circuit Testing by John P. Hayes, Debashis Bhattacharya

160 pages missing pub info (view editions)

nonfiction computer science design informative medium-paced
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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate i...

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